Mastering RISC-V in SystemVerilog: From ISA to Working CPU

Descripción

Are you ready to move beyond theory and actually build a working processor? This course takes you step by step through designing, coding, and simulating a fully functional RISC-V RV32I single-cycle processor. We start from the fundamentals of the RISC-V architecture and gradually construct every hardware block: Instruction Memory, Fetch, Decode, Register File, ALU, Data Memory, Branch Control, and the Control Unit. You’ll see how each piece works on its own, and how they all connect into a real CPU capable of running machine code. Unlike theoretical architecture courses, this one is hands-on and project based. You won’t just learn how a processor works, you will build one, simulate it in ModelSim, load assembly programs, and watch them execute. By the end of this course, you will: • Understand the RISC-V ISA deeply - instruction formats, immediates, registers, and execution flow. • Design every CPU block in SystemVerilog and connect them into a complete RV32I processor. • Decode real instructions and generate all associated control signals. • Run assembly algorithms such as Maximum Finder, Fibonacci, and Bubble Sort on your processor. • Simulate and debug the entire CPU in ModelSim with waveform analysis. • Think like a hardware architect - understanding datapaths, control logic, and instruction execution. This course is perfect for: • Students in Computer Engineering or Electrical Engineering who want real CPU-design experience. • Beginners in digital design seeking a guided, practical introduction to processor architecture. • Junior Design and Verification Engineers who wants to understand how a real processor works at the RTL level. No prior RISC-V experience is required. Basic Verilog/SystemVerilog knowledge is required, and everything else is taught step by step, from architecture to simulation. Join now, and let’s build a complete RISC-V processor together!

Lo que aprenderás

• Build a complete RISC-V 32I single-cycle CPU from scratch using SystemVerilog.
• Design every major processor block, including ALU, Register File, Control Unit, and Memory.
• Understand the RISC-V instruction set, how instructions are encoded, and how software translates into hardware operations inside the CPU.
• Run assembly programs on a fully functional RISC-V processor and execute real algorithms, including Finding Maximum Value, Fibonacci, and Bubble Sort.
• Design and integrate a custom Instruction Set Extension (ISE) into a RISC-V processor to accelerate real programs

Requisitos

• An interest in digital logic, processors, or computer architecture, and the motivation to learn by actually building and running a real RISC-V processor.
• Familiarity with SystemVerilog (modules, signals)
• Understanding of binary and hexadecimal numbers.