Digital Design with SystemVerilog HDL + Introduction to UVM

Descripción

Master SystemVerilog Fundamentals through Hands-On Circuit Design Are you ready to take your first steps into the world of digital design and verification? This course gives you the practical skills and confidence to move from theory to working designs — all through SystemVerilog. We’ll start from the very basics and progress step by step, covering the essential building blocks of digital systems: multiplexers, encoders, ALUs, registers, finite state machines, and memory. Every topic includes clear explanations, practical coding examples, and simulation in ModelSim so you can see how theory transforms into working circuits. Unlike other courses, this one is hands-on and project-based. You won’t just watch code — you’ll write it, simulate it, and solve real problems, just like in the industry. By the end of this course, you will: • Master HDL fundamentals: Learn the three main modeling styles — dataflow, behavioral, and structural. • Write clean RTL code: Develop synthesizable SystemVerilog for real designs. • Understand the design flow: From architecture to RTL and simulation. • Design key digital circuits: Implement and verify MUXes, Adders, priority encoders, ALU, registers, counter, FIFO, FSMs, and single-port RAM. • Final Project : Serial Communication System • Introduction to UVM (Universal Verification Methodology) • Build confidence: Learn not just what to write, but how to think like a design engineer. This course is perfect for: • Students in Electrical and Computer Engineering who want to strengthen their HDL foundations. • Beginners in digital design who want a guided, hands-on approach. • Junior engineers preparing for technical interviews in VLSI, ASIC, or FPGA design. No prior experience in SystemVerilog is required. A basic understanding of logic gates and binary operations is enough — everything else is taught step by step. Join now, and let’s start building digital systems together!

Lo que aprenderás

• Gain a solid understanding of HDL fundamentals using SystemVerilog.
• Understand the ASIC and FPGA design flow from high-level architecture through RTL design and simulation with ModelSim.
• Be able to write clean, synthesizable SystemVerilog code using dataflow, behavioral, and structural styles
• Learn how to design combinational logic circuits (MUX, Adders, Priority Encoder, ALU).
• Learn how to design sequential logic circuits (Register, Counter, FIFO, FSMs and single-port RAM memory).
• Students will learn to design a digital systems in SystemVerilog, completing a TX/RX Serial Communication project for their portfolio.
• Introduction to UVM (Universal Verification Methodology)

Requisitos

• Motivation and curiosity to learn Digital Design!
• Basic knowledge of digital logic components such as logic gates (AND, OR, NOT), truth tables, multiplexers, decoders, and simple sequential elements like flip-flops.
• Some programming experience (e.g., C, C++, or Python) is helpful but not required, it will make it easier to adapt to the coding aspects of hardware description languages.