Complete ASIC Design Flow: VLSI From Idea to Silicon

Descripción

USE PROMO "PAY.13 " No prior VLSI experience? No problem. This course is designed to take you from absolute beginner to an engineer capable of designing a complete, complex system chip—all the way from digital logic to a tape‑out ready GDSII file. Most courses teach isolated pieces: a bit of Verilog, some timing, or a tool. This one is different. We walk you through the entire ASIC design flow in a structured, step‑by‑step way, assuming no background in chip design. You’ll start by understanding what a transistor is and how digital circuits work. Then, you’ll learn Verilog HDL through dozens of labs and assignments, progressing from simple counters to a 16‑bit ALU, register files, and finite state machines. But front‑end RTL is only the beginning. We then dive into the critical implementation stages: TCL scripting to automate flows, Static Timing Analysis (STA) to fix setup/hold violations, low‑power design techniques used in modern mobile chips, and logic synthesis where RTL is transformed into gates. You’ll also master Clock Domain Crossing (CDC) with asynchronous FIFOs, Design for Test (DFT) with scan chains, and formal verification to ensure equivalence. All of this culminates in a final system assignment—a UART‑based subsystem with a register file and ALU, which you then take through the physical design (PnR) flow using Cadence tools, ending with GDSII export. By the end, you will have built a chip from the ground up, with a portfolio project that proves your skills.

Lo que aprenderás

• Digital Fundamentals: From CMOS logic families and gate‑level behavior to delay and power (dynamic, leakage).
• Verilog HDL: Write RTL for counters, ALUs, FSMs, register files, and testbenches—no prior coding experience needed.
• TCL Scripting: Automate constraints and flows—an essential skill for CAD and backend engineers.
• Static Timing Analysis (STA): Perform setup/hold analysis, identify critical paths, and fix violations.
• Low‑Power Design: Implement clock gating, operand isolation, multi‑VT, and power gating.
• Logic Synthesis: Convert RTL to gate‑level netlists using industry‑style constraints and libraries.
• Clock Domain Crossing (CDC): Handle metastability, data incoherence, and design asynchronous FIFOs with depth calculation.
• Design for Test (DFT): Insert scan chains and improve testability.
• Formal Verification: Run equivalence checking with Synopsys Formalit
• Physical Design (PnR): Complete floorplanning, power planning, placement, CTS, routing, and chip finishing using Cadence; export GDSII.

Requisitos

• No prior VLSI or hardware knowledge required. We start from the very basics.
• Basic computer literacy – you should be comfortable installing software and using a web browser.
• A computer with internet access and Linux virtual machine inastalled on it for EDA tools.
• Willingness to learn – that’s it. Everything else is taught from the ground up.