ASIC Synthesis-STA-Physical Design(PD):Cadence+Synopsys flow

Descripción

Section 1: Synthesis and Static Timing Analysis (STA) This course is intended for all levels of students, who want to gain knowledge in ASIC synthesis and STA. Electronics students, who want to internships, Engineers who want to start career in VLSI field. The course covers the following chapters: 1. ASIC flow in brief 2. Logical synthesis Part 1 - inputs and outputs of synthesis, synthesis constraints, Libraries 3. Logic Synthesis Part II - Synthesis demo using Cadence Genus tool flow 4. Physical Synthesis - Various file formats and descriptions, Physical dimensions of gates 5. Timing concepts - Setup time, hold time, slack. violations, timing budgets 6. Static Timing Analysis - 7. Timing paths - Clock to output, propagation delay, input delay, output delay etc, STA using Cadence Tempus tool flow 8. Timing constraints and various modes - MMMC 9. Timing Exceptions - False path, multi cycle path 10. Synthesis and STA assignment - APB Timer Section 2: Physical Design Flow using Cadence Tools - APB UART Design 11. Inputs to Physical Design 12. Innovus Tool Steps 13. Floorplan 14. Floorplan demo 15. Placement 16. CTS 17. CTS Demo 18. Routing 19. SDC_MMMC_PVT Corners 20. Physical Verification 21. Physical design assignment using cadence innovus flow - APB Timer design Section 3: Physical Design Flow using Synopsys Tools - RISCV Processor Design 22 DC Synthesis 23. ICC2 Flow Introduction 24. ICC2 Initialization 25. ICC2 Floorplan 26. ICC2 PowerPlan 27. ICC2 Placement 28. ICC2 CTS 29. ICC2 Routing & Chip Finishing 30. PrimeTime - Post Layout STA 31. Formality - Logic Equivalence Check (LEC) 32. Synthesis and Physical Design Assignment using Synopsys tools - This course is intended for all levels of students, who want to gain knowledge in ASIC synthesis and STA. Electronics students, who want to internships, Engineers who want to start career in VLSI field. The course covers the following chapters: All the topics are elaborated with detailed examples, illustrated with diagrams, where required. Clear explanation; assignments added at the end of the course for practicing hands on examples. The lecture is given by hands on practitioners from the VLSI industry, who have worked on multiple projects and taped out chips For best take away from the course, kindly do hands on using tools (may be available in your institutions/companies). All the best - Happy learning

Lo que aprenderás

• ASIC Flow in brief
• Logical Synthesis vs Physical Synthesis
• Timing Concepts, definitions
• Static Timing Analysis (STA)
• Timing paths, Contraints, modes
• Synthesis example execution with Genus tool
• STA example execution with Tempus tool
• Physical design flow using Innovus tool
• Floorplan
• Placement
• Clock Tree Synthesis (CTS)
• Routing

Requisitos

• Basics of RTL design using Verilog
• Digital Fundamentals
• Verilog Language